EECS 579, Fall 2002 Digital System Testing Project Report

Comprehensive Study on Designing Memory BIST: Algorithms, Implementations and Trade-offs

By: Allen C. Cheng

Advanced Computer Architecture Lab Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor, MI 48109-2122 [email protected]

Date: December 16, 2002

Table of Contents 1. 2. 2.1. 2.2. 3. 3.1. 3.2. 4. 4.1. 4.2.

4.3.

5. 6. 6.1.

6.2.

6.3.

6.4.

7. 8. 9.

Preface................................................................................................................. 1 Introduction......................................................................................................... 1 Motivation........................................................................................................... 1 Background ......................................................................................................... 2 Algorithms .......................................................................................................... 3 Classical Test Algorithms.................................................................................... 4 March-based Test Algorithms ............................................................................. 4 Implementations.................................................................................................. 5 Hardwired-based BIST ....................................................................................... 5 Microcode-based BIST ....................................................................................... 6 4.2.1. Background ......................................................................................... 6 4.2.2. Approach............................................................................................. 6 4.2.3. Design ................................................................................................. 7 4.2.4. Conclusions......................................................................................... 9 Processor-based BIST ....................................................................................... 10 4.3.1. Background ....................................................................................... 10 4.3.2. Approach............................................................................................11 4.3.3. Design ............................................................................................... 12 4.3.4. Conclusions....................................................................................... 13 Trade-offs.......................................................................................................... 13 Innovations........................................................................................................ 14 Defect Coverage as a New Measure for Test Quality....................................... 14 6.1.1. Main Idea .......................................................................................... 14 6.1.2. Background ....................................................................................... 15 6.1.3. Approach........................................................................................... 15 6.1.4. Conclusions....................................................................................... 18 Integration of Diagnostics................................................................................. 19 6.2.1. Main Idea .......................................................................................... 19 6.2.2. Background ....................................................................................... 19 6.2.3. Approach........................................................................................... 21 6.2.4. Conclusions....................................................................................... 22 Automatic Generation of Memory BIST using Compiler ................................ 23 6.3.1. Main Idea .......................................................................................... 23 6.3.2. Background ....................................................................................... 23 6.3.3. Approach........................................................................................... 24 6.3.4. Conclusions....................................................................................... 26 Built-in Self-Repair using Redundant Words ................................................... 26 6.4.1. Main Idea .......................................................................................... 26 6.4.2. Background ....................................................................................... 26 6.4.3. Approach........................................................................................... 27 6.4.4. Conclusions....................................................................................... 30 Future Direction ................................................................................................ 30 Conclusions....................................................................................................... 31 References......................................................................................................... 32

i

Comprehensive Study on Designing Memory BIST: Algorithms, Implementations and Trade-offs Allen Cheng Advanced Computer Architecture Lab Electrical Engineering and Computer Science Department The University of Michigan Ann Arbor, MI 48109 [email protected]

1.

Preface This report presents a compressive study on designing memory BIST.

The study

covers motivation behind memory BIST, algorithm of different test patterns, surveys of current memory BIST architecture, and discussion of various implementation issues.

It

is my best intention that this report will serve as a knowledge base for future design in memory BIST. The remainder of this report is organized as follows: Section 2 introduces the motivation and background of memory BIST.

Section 3 describes the algorithms of

various memory tests. Section 4 and 5 present different implementation schemes and their design trade-offs.

Section 6 investigates some innovative techniques from both

industry and academia.

The conclusions and future direction of memory BIST are

offered in Section 7 and 8.

2. Introduction This section gives the motivation and background behind memory BIST.

2.1. Motivation Memories are the most universal component today. 1

Almost all system chips

contain some type of embedded memory, such as ROM, SRAM, DRAM, and flash memory.

In the realm of PC, Alpha 21264, for example, has cache RAMs that represent

2/3 of total number of transistors in use and 1/3 of total chip area. In the embedded domain, embedded RAMs of the StrongArmSA110 occupy 90% of the total area. (Bhavsar, ITC-99)

The projection is, by 2010, memory will represent more than 90% of

the chip area in average SOC environment. (ITRS 2000) With the advent of deep-submicron VLSI technology, the memory density and capacity is growing.

The clock frequency is never higher.

The dominant use of

embedded memory cores along with emerging new architectures and technologies make providing a low cost test solution for these on-chip memories a very challenging task. Built-in self-test (BIST) has been proven to be one of the most cost-effective and widely used solutions for memory testing for the following reasons: (1) No external test equipment; (2) Reduced development efforts; (3) Tests can run at circuit speed to yield a more realistic test time; (4) On-chip test pattern generation to provide higher controllability and observability; (5) On-chip response analysis; (6) Test can be on-line or off-line; (7) Adaptability to engineering changes; (8) Easier burn-in support.

2.2. Background There are two types of BIST: On-line and Off-line.

On-line BIST has tests

implemented on-chip. It has shorter test time but an area overhead of one to three percent.

Off-line BIST, on the other hand has tests implemented off-chip.

It has

longer test time but no area overhead. On-line BIST can further be classified into three subgroups: Concurrent BIST, Non-Concurrent BIST, and Transparent BIST. 2

Concurrent BIST is a memory test

mechanism where the memory can be tested concurrently with normal system operation. Thus, it has instant error detection and possible correction, but all faults will be detected within the restrictions of the method used. There is also certain hardware overhead associated with this scheme.

For example, we need logic to write out, read in, and store

redundant information generated during the test process. There will also incur certain performance penalty upon every memory access. Non-Concurrent BIST is test mechanism that requires interruption of the normal system function in order to perform tests; usually a special test mode is required. The advantage is there is no need to preserve the data yields certain space savings. The disadvantage is the circuit cannot detect faults that are not covered by the fault models used.

Transparent BIST scheme is very similar to the Non-Concurrent scheme except

the memory contents are preserved.

3. Algorithms A test algorithm is a finite sequence of test elements.

A test element contains a

number of memory operations (access commands), data pattern (background) specified for the read operation, address (sequence) specified for the read and write operations. Table 3-1 gives summary of various test algorithms that have been actually implemented in modern memory BIST circuitries.

We divided these test algorithms into two groups:

Classical tests and March-based tests.

3

Algorithm

Fault coverage AF SAF TF CF Others

Zero-One Checkerboard Walking 1/0 GALPAT GALROW GALCOL Sliding Diag. Butterfly

L L LS LS LS

L L L L L L L

L L L L L

L L L L -

MATS MATS+ Marching 1/0 MATS++ March X March CMarch A March Y March B

DS D D D D D D D D

D D D D D D D D D

D D D D D D D

D D D D D

Unlinked CFins Unlinked CFins Unlinked CFs Linked TFs Linked CFs

D D D

D D D

D D D

D D D

Read access time 3-coupling faults Operational faults

MOVI 3-coupling Paragon L = Locate

Refresh Sense amplif. rec. Write recovery Write recovery Write recovery

LS = Locate some

D = Detect

Test time Order

1M mem.

O(n) O(n) O(n^2) O(n^2) O(n• v n) O(n• v n) O(n• v n) O(n•log 2n)

0.42s 0.52s 2.5d 5.1d 7.2m 7.2m 10s 3.6m

O(n) O(n) O(n) O(n) O(n) O(n) O(n) O(n) O(n)

0.42s 0.52s 1.5s 0.63s 0.63s 1.0s 1.6s 0.85s 1.8s

O(n•log 2n) O(n•log 2n) O(n^2)

3.3h 54s 20d

DS = Detect some

Table 3-1: Summary of Memory Test Algorithms

3.1. Classical Test Algorithms Classical test algorithms are either (1) simple, fast but have poor fault coverage, such as Zero-one, Checkerboard; or (2) have good fault coverage but complex and slow, such as Walking, GALPAT, Sliding Diagonal, Butterfly, MOVI, and etc.. Due to these imbalanced conflicting traits, the popularity of these algorithms is decreasing.

3.2. March-based Test Algorithms A March-based test algorithm is a finite sequence of March elements. element is specified by an address order and a number of reads and writes.

4

A March

Examples of

some March-based tests are MATS, MATS+, Marching 1/0, March C-, March Y, March A, March B, and etc.. Since March-based tests are all simple and possess good fault coverage, they are the dominant test algorithms implemented in most modern memory BIST.

4. Implementations This section describes different implementation schemes for memory BIST.

A

memory BIST unit consists of a controller to control the flow of test sequences and other components to generate the necessary test control and data.

In this project report, the

various types of memory BIST are categorized according to the schemes of their controllers. Designs of a memory BIST controller could be roughly classified into three different types: (1) a hardwired-based, (2) microcode-based, and (3) processor-based. There are two major paper designs discussed in detail.

The following three subsections

give the specifics of each scheme.

4.1. Hardwired-based BIST

Hardwired FSM

Figure 4-1: Hardwired-based Memory BIST 5

A hardwired-based controller is a hardware realization of a selected memory test algorithm, usually in the form of a Finite State Machine (FSM).

This type of memory

BIST architecture has optimum logic overhead, however, lacks the flexibility to accommodate any changes in the selected memory test algorithm.

This results in

re-design and re-implementation of the hardwired-based memory BIST for any minor changes in the selected memory test algorithm.

Although it is the oldest memory BIST

scheme amongst the three, hardwired-based BIST is still much in use and techniques have been kept developing.

4.2. Microcode-based BIST 4.2.1. Background A microcode-based memory BIST features a set of predefined instructions, or microcode, which is used to write the selected test algorithms. loaded in the memory BIST controller.

The written tests are

This microcode-based type of memory BIST

allows changes in the selected test algorithm with no impact on the hardware of the controller. This flexibility, however, may come with the cost of higher logic overhead for the controller. A very recent microcode-based memory BIST implementing modified march algorithm was proposed in [1].

There are two objectives of this design: (1) to enhance

the detection boundary by capturing CMOS ADOF and NPSF faults; (2) to minimize the microcode storage by using a ROM and a small register file. 4.2.2. Approach The approach of this microcode-based design is to focus on capturing Address 6

Decoder Open Faults (ADOF) and detecting some NPSFs in addition to the conventional SF, TF, CF, DRF faults. ADOF are caused by open defects in the CMOS logic gates of the memory address decoders and, due to their sequential behavior, cannot be mapped to faults of the memory array itself, hence it cannot be detected by conventional march algorithms.

As a result, this paper modified the conventional march tests by changing

the order of memory addresses generation to produce three consecutive march elements. One technique introduced here is to adopt the Cellular Automata (CA) based address generator and random pattern to enhance the detection boundary to pattern sensitive faults.

One example of CA based address generators is Linear Hybrid Cellular

Automata (LHCA).

It is implemented by combining transition matrix and Linear

Feedback Shift Register (LFSR) of Linear Cellular Automata (LCA).

LHCA

determines the next state of a cell dependent upon the current states of the cell itself and its neighboring cells.

LHCA has superior randomness than LFSRs and it is widely used

for BISTs and cryptography. 4.2.3. Design

Figure 4-2: Microcode-based BIST [1] 7

Figure 4-2 illustrated a microcode-based memory BIST which consists of storage unit, instruction counter, instruction decoder, LHCA address generator, and comparator. The storage unit is a 6x10 bits ROM that stores the conventional march test algorithms. The instruction counter is a log2(X)+1 bit binary up-down counter which selects the instruction address of the ROM.

It is initialized by a test enable signal and terminated

by a test end signal after the last instruction has been executed.

The instruction decoder

generates the up-down address and hold/enable signals by taking the instruction condition bits and LHCA terminal signals.

The up-down LHCA is a randomly inversed LHCA

that is generated to generate 2000 independent random address pattern in hope to provide better NPSF coverage. Finally, the comparator produces an error signal by comparing the test data and RAM output data. The microcodes associated with each March operations and the corresponding control signals are described in the figure below.

Figure 4-3: March test procedure and microcodes [1] The following table shows the size of a ROM required if each March test is 8

performed independently.

Table 4-1: Microcode storages required by different march algorithms [1] Among the March algorithms, only the MARCH A algorithm is stored into the 50 bits ROM and different march tests are performed by giving the sequence number of the March operations into the 21x4 bits register file.

The results of this technique requires

approximately only one third of the other micro-code storages as shown in the table below.

Table 4-2: Comparison of microcode storages [1] 4.2.4. Conclusions The authors conclude that compared with previous microcode-based memory BISTs, their design requires only one third of microcode storages of others. In addition to conventional static and retention faults, it can also detect ADOFs and NPSFs with

9

cellular automata based address generator.

The proposed memory BIST can be widely

used for the embedded memory testing, especially under SOC design environment because of its superior flexibility and extendibility in applying different combination of memory test algorithms.

4.3. Processor-based BIST 4.3.1. Background With the introduction of deep-submicron VLSI technology, core-based SOC design is attracting an increasing attention. On an SOC, memories are the most universal cores: almost all system chips contain some type of embedded memory, such as ROM, SRAM, DRAM, and flash memory.

To provide a low cost test solution for these on-chip

memory cores is a challenging task. Conventional hardwired-based memory BIST approach is one possible solution and its advantage are short test time and small area overhead. However, sometimes it is not feasible to have one BIST circuit for each memory core.

For instances, a typical ASIC

or SOC may have tens of SRAM cores with different sizes and configurations.

If each

memory core on chip requires a BIST circuit, then the area and test pin overhead will be unacceptably high.

Therefore, a new type of memory BIST scheme which utilizes an

on-chip microprocessor to test the memory cores was proposed [2].

10

Figure 4-4: Processor-based memory BIST [2] The processor-based memory BIST is done by executing an assembly-language program in the on-chip microprocessor to generate test patterns including the address sequence, data patterns, and control signals. with the expected correct data.

The memory outputs are then compared

The advantage of such a scheme is that it is highly

flexible because various test algorithms can be realized by simply modifying the assembly programs run on the microprocessor and it is also easy to support testing of multiple memory cores. However, the drawback is a much longer test time. 4.3.2. Approach A modified processor-based scheme was proposed in [3].

It utilizes a

processor-programmable BIST circuit to realize a test algorithm using pre-defined test elements.

The approach is a combination of on-chip processor-based BIST and the

hardwired-based BIST.

The proposed scheme has the following advantages: (1) the test

time is short due to dedicated BIST core; (2) the flexibility of processor-based BIST is maintained; and (3) multiple memory cores can be supported without multiple BIST cores, multiple sets of external test pins, or complicated routing. 11

4.3.3. Design As shown in Figure 4-5, the BIST core is inserted between the CPU core and the on-chip bus, which also connects the memory cores.

In normal operation mode, the

CPU transparently accesses the system bus with slight time overhead introduced by the multiplexers.

The overhead can be minimized by careful design of the multiplexers

which can be integrated with the bus drivers. In memory BIST mode, the BIST circuitry takes over the control of the on-chip bus.

It executes certain test algorithm programmed

by the CPU and generates the addresses, input data, and control signals of the memory core.

It also compares the memory output response with the expected correct data. In

order to allow these two different modes, several multiplexers are used to multiplex the address bus, data input bus, data output bus, and control bus between the CPU core and the BIST circuitry.

Figure 4-5: Modified Processor-based Memory BIST Architecture [3] The block diagram of the BIST circuit is shown in Figure 4-6.

There are several

registers in the BIST circuit that are used to store necessary information during the memory BIST process or store the memory test result.

Other blocks in the BIST circuit

include: (1) an address counter which generates the test address sequence; (2) a 12

comparator which compares the memory output response with the expected correct data; and (3) a BIST controller which controls the BIST circuit.

Figure 4-6: Modified Processor-based Memory BIST Circuitry [3] 4.3.4. Conclusions We have seen a flexible and cost-effective memory BIST scheme for single or multiple memory cores in the SOC environment where an on-chip processor is available. The design is flexible because different memory test algorithms can be realized by executing proper assembly programs on the on-chip processor core. It is cost-effective because the test time is short and the hardware overhead is low.

In addition, there is no

need to modify the CPU nor the memory with the proposed BIST, thus the design cost is reduced.

5. Trade-offs This section presents the various design trade-offs among the three implementation schemes.

Table 5-1 gives the summary of this comparison.

13

Scheme

Test Time Area OH Routing OH Flexibility

Hardwired short

low

high

zero

Microcode

average

high

low

low

Processor

long

zero

zero

high

Table 5-1: Trade-offs between Different Memory BIST Schemes The four evaluation metrics used are: test time, area overhead, routing overhead, and flexibility. The routing overhead is directly translated into design efforts and time to market.

The flexibility is expressed in terms of programmability of algorithms and

adaptability to engineering changes.

As shown in the table, the Hardwired-based BIST

is fast, compact, incur the most design efforts and possesses the least flexibility.

On the

opposite end of spectrum, the Processor-based BIST is the most flexible, zero area or routing overhead, but incur long test time. The Microcode-based designs is somewhere in between these two extreme prototypes.

6. Innovations This section presents the novel design aspects for modern memory BIST.

These

various innovations took different points of view to improve the design of memory BIST including change in algorithm, add-on technique, and renovated architecture.

Four

papers are presented in details in the following subsections.

6.1. Defect Coverage as a New Measure for Test Quality 6.1.1. Main Idea The main idea is to use defect coverage, rather than fault coverage, as our new

14

metric to measure the quality of the memory test algorithms [4].

The rationale is that

since there is no linear correspondence between fault coverage and defect coverage, and defect coverage provides a better estimate for overall test quality in terms of defects-per-million of shipped parts; therefore, test engineers should measure the quality of memory tests by their defect coverage rather than fault coverage. 6.1.2. Background The motivation behind this paper comes from the fact that most BIST structures are fixed and cannot be modified once committed to silicon. Therefore, BIST designers must ensure that the test algorithms embedded in the BIST structures are able to provide a high level of coverage for the given memory designs.

Until now (2002), there has been

no generally accepted metric for measuring memory test coverage that has a high correlation to quality (DPM) and yield. The authors use the defect coverage assessments provided by the Safari™ system as a measure of memory test quality. Safari is a simulation tool that uses Inductive Fault Analysis (IFA) to determine the set of realistic failures for a memory and the percentage of defects that are associated with each failure. The percentage of detected defects is directly used to estimate yields using well-established models.

The results can then be

used to guide the development of better test sets as measured by fault coverage and yield. 6.1.3. Approach The memory device that was analyzed is a 6-port commercial embedded SRAM targeted for a 0.13µ process.

It has 1 write port and 5 read ports. The memory was

organized such that a complete row was accessed for every read and write; thus, only a

15

row address was needed to access the array.

The 4 tests applied to the memory are:

z

4n Checkerboard scan (checker)

z

Galpat test (galpat)

z

5n March with forward LFSR addressing order (march)

z

5n March with reverse LFSR addressing order (march rev)

Safari runs HSpice, an analog transistor-level simulation, to determine the faulty behaviors caused by the realistic faults. The faults are modeled by simple resistor circuits: 1Ω for shorts and 10Ω for opens. The fault extraction results are shown in Table 1 that tells us two things: (1) despite open faults comprising 25% of the extracted faults, a vast majority of the defects cause short faults to occur; (2) there is no one-to-one correspondence between the percentage of faults and the percentage of random defects that can cause these faults.

Table 5-1: Percentage of fault types extracted from the memory layout [4] The percentage of weighted critical area (WCA) associated with each fault type is the percentage of random defects that can cause these faults. The WCA is computed by multiplying the critical area extracted from the layout and its weight given by Equation 5-1 where wi is the width of the bar used to approximate the defect density curve at

16

defect size xi, and ki is a weighting factor for different defect mechanisms as listed in Table 5-2.

Equation 5-1: Weight of Critical Area [4]

Table 5-2: Weighting factors of different defect mechanisms [4] The fault and defect coverage results for each for the four tests are summarized in Table 3.

The data in the table assumes that only one test is run at a time.

shows, all of the tests achieve fault coverage of about 90%.

As the table

While the galpat test

achieves the highest fault coverage, the checkerboard test achieves slightly higher defect coverage than that of galpat.

The small difference between the fault and defect coverage

of the two march tests tells us that the sets of faults detected by these two march tests are different.

17

Table 5-3: Fault and defect coverage of the four tests [4] This different fault and defect coverage between the two march tests is due to the various levels of address and data scrambling that is often present in memory designs. The addresses and data organization often changes between the “logical” view of the memory, the “physical” view of the memory, and finally the “topological” view of the memory.

These changes of data organization can cause bits that are logically adjacent

to be distributed across a physical array of cells.

Or even further, the topological

placement of the cells may cause changes to the polarity of the data stored in the actual memory cells.

In short, these scrambling effects can hamper the effectiveness of tests

unless the data patterns and address sequences in the test account for the various scrambling features in the memory. 6.1.4. Conclusions This paper shows defect-oriented metric as a better measure for the quality of memory tests.

While fault coverage is useful to the test engineers in the process of

design and development of tests, because there is no linear correspondence between fault coverage and defect coverage, thus fault coverage is not a good indicator of test quality. Defect coverage, on the other end, provides a better estimate for overall test quality in terms of defects-per-million of shipped parts.

18

6.2. Integration of Diagnostics 6.2.1. Main Idea The main idea of [5] is to integrate full diagnostic capabilities into existing memory BIST designs to allow both effective and efficient manufacturing test by isolating faults incurred during the manufacturing or design process.

The technique

improves the overall satisfiability of the cost, quality, and time to market requirements of embedded memory and is used for a wide range of PowerPC™ microprocessors. The author uses 6-transistor SRAM designs to illustrate this technique and he claims that it can also be used in other types of volatile and nonvolatile memories. 6.2.2. Background The author starts the discussion by defining a set of design objectives for integration of memory BIST into embedded memories with diagnostics, which includes: z

Effective memory test algorithm

z

Ability to perform test efficiently

z

Integration of diagnostics

z

Minimize impact to die area

z

Minimize impact on memory performance

z

Minimize test system requirement

z

Ability to operate at operating frequency

z

Ease of use

z

Reuse of design

Following the design objectives is an overview of various embedded memory test 19

techniques including: (1) Functional pattern memory testing, (2) Direct memory test access, (3) Direct scan access, (4) Random pattern memory BIST, and (5) Deterministic memory BIST. The author uses the deterministic memory BIST scheme, because he claims that it is very widely used and analyzed throughout the industry and both its effectiveness and efficiency have been demonstrated repeatedly.

Figure 5-1: Memory BIST block diagram [5] The overview of test techniques is followed by a description of the author’s memory BIST design.

The deterministic memory BIST is based on the March C memory test

algorithm due to its efficiency (test duration), effectiveness (quality of test), plus its ease of use, implementation, and diagnostics. generated locally for each memory.

All input data for the memory BIST is

The data patterns are selected to ensure each bit cell

is surrounded by complement data regardless of its physical orientation. The memory outputs are compared against the expected data, which is determined by the present algorithm state and which of the two read operation is occurring. A single pass/fail

20

status bit is generated from the logical OR of 16 bit compares, which is output directly to the device pins for BISTMAP comparisons, and latched into the memory BIST status sticky bit. The above block diagram illustrates the entire memory BIST design. 6.2.3. Approach The integration of diagnostics with the memory BIST is finally described. Each of the memory analysis and diagnostic techniques are simple extensions to the existing memory BIST structure. The memory BIST with integrated diagnostics can detect, isolate and diagnose a failure when used in conjunction with a post-processing routine. Since the logical address of a specific memory bit may not align to its actual physical position due to changes necessary to balance power and performance characteristics, a logical to physical transformation, called bitmapping, occurs on the fail memory data to generate a topologic cal map of the physical memory.

Static

bitmapping maps the internal memory bit cells by statically applying the input controls, address, data, read/write and clocks. Dynamic bitmapping generates a memory fail bitmap by applying a set of sequential operations. There are three types of diagnostic techniques: (1) Direct access, (2) Scan access, and (3) BISTMAP. Direct access is a test scheme that allows for both static and dynamic bitmapping of an embedded memory.

It includes the following two steps:

On-line production diagnostic monitoring is implemented by bringing the parallel data from the memory out to the external pins of the device, allowing the concurrent mapping of the as the test progresses through the memory test algorithm sequence. 21

Fail data post-processing performs the final transformation from the logical to physical mapping of the memory. The entire diagnostics sequence allows concurrent, real time bitmapping and diagnostic of embedded memories. The limitation is its operating frequency and accuracy, because the device pins are used to stimulate the memory. Scan access is an integration of scanning capability into the memory BIST device that enables effective testing of the logic surrounding the memory, in addition to controlling and observing the inputs and outputs of the memory directly. Since all latch elements are able to be directly scanned and controlled, it has the ability to apply any address and data sequence, which allows for both static and dynamic bitmapping and diagnostics to occur.

The limitation comes from the high complexity and long duration

of applying complete and correct test sequences which makes it useful only in the most cost insensitive manufacturing step, such as an off-line failure analysis environment. BISTMAP is an extension to the memory BIST.

It has mechanism similar to the

direct access diagnostics, but with further reduced external pin requirement. memory BIST is run through one complete sequence. dynamically captured on each memory read operation. be detected when it occurred.

The

the output status bits are

The failure would immediately

Algorithmically the failing sequence and fault mechanism

are identified. 6.2.4. Conclusions Integration of diagnostics into a memory BIST is a simple extension to the existing logic.

Addition of few simple controls and observation points can enhance a memory

BIST, to achieve all manufacturing, design and diagnostics needs, without compromising 22

any of the other requirements.

6.3. Automatic Generation of Memory BIST using Compiler 6.3.1. Main Idea The objective of [6] is to minimize test effort for embedded memories in SOC by enabling automatic test integration of multiple and heterogeneous memory cores in a SOC environment.

The authors present an automatic generator for memory BIST

circuits called BRAINS (BIST for RAM in Seconds).

It has a graphic user interface and

is integrated with a memory compiler to form an IP generator for various memory configurations.

It also features an automatic test grouping and scheduling which can

optimized the overhead in test time, performance, and power consumption.

With a

configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators. 6.3.2. Background Memory testing is becoming the dominant factor in testing a system-on-chip, with rapid growth of the size and density of embedded memories.

In a typical SOC design,

the number of memory cores range from tens to even hundreds, with a wide array of memory types and configurations. Test integration, therefore, has become an important issue in managing the BIST circuits, test activation, and response collection and analysis. Most of the previous works focused on the design of the BIST architecture instead of the memory test integration at the system level. Therefore, [6] proposed a new version of automatic generator for memory BISR circuits, which targets automatic test integration of multiple and heterogeneous memory cores in an SOC environment in order to minimize 23

the test effort. 6.3.3. Approach

Figure 5-2: BIST architecture for multiple memory cores [6] The new BIST architecture for multiple memory cores is shown in Figure 5-2. external tester can access all the memories via a single shared BIST controller. more sequencers can be used to generate March-based test algorithms.

The

One or

Each TPG

attached to the memory will translate the March-based test commands to the respective RAM signals.

Figure 5-3: TGS algorithm [6]

24

The authors also propose test grouping and scheduling (TGS) algorithm to facilitate the BIST generation under various test constraints, such as time and power.

The

purpose of test grouping the scheduling is to minimize the overall testing time for all the memory cores, given limited test resources. The summary of the TGS algorithm is given below and its flow is depicted in Figure5-3.

Figure 5-4: BRAINS [6] The block diagram of BRAINS is depicted in the Figure 5-4.

The user generates

the BIST circuit using the GUI or command shell and evaluates the memory test efficiency among different designs easily. BRAINS can be integrated with a memory compiler to deliver BISTed memory IPs. The BIST Intermediate Description (BID) Constructor translates the user-defined parameters to an internal memory specification and test requirement file. Common memory specifications are predefined in the memory library.

The user can access

existing memory objects and construct the target one with slightly modification.

Using

the presented BIST architecture as the template, the compiler generates the BIST design, control signals, and necessary scripts for synthesis and integration. integrated into an existing logic design flow easily.

25

The process can be

With TGS, test time can be further

reduced, under certain given constraints.

The rapid generation process makes the

system handy at the early design phase of a system chip. 6.3.4. Conclusions The automatic generation of memory BIST cores extends the ability of system-level test integration, multi-port and multi-memory support, and test grouping and scheduling for parallel testing.

The BIST access can be parallel for easy test control, or serial for

simple IO interface, depending on the test requirement.

The proposed BRAINS

generates configurable and extensible BIST circuits, and performs test grouping and scheduling, as well as overall test planning of embedded memory cores for SOC designs in a cost-effective way.

6.4. Built-in Self-Repair using Redundant Words 6.4.1. Main Idea The design [7] proposes a word oriented memory Built-in Self-Repair methodology (BISR) that targets on embedded SRAM and does not rely on spare rows and columns. It uses BIST logic to identify faulty words and redundancy logic to store faulty addresses and data immediately after its detection during test; wrapper logic to replace defect words. 6.4.2. Background The motivation behind this approach argues that as the complexity of today’s deep submicron technology grows unmanageable, and the implementation of a large number of memories on a single chip becomes feasible, BIST along is no longer sufficient to acquire 26

the desired level of yield and reliability.

Using BISR in addition to BIST is essential in

improving the overall reliability of memories and total chip yield with its added repairabilility. In typical memory BISR design, redundant spare rows and spare columns are often included in to the memory.

However, using this row and column structure is justified

only if majority of faults are row and column faults, e.g. DRAMs.

Since the authors

want to focus on SRAMs and faults in SRAMs often affect only single bits or a neighborhood thereof, they argue that this word oriented design is more efficient and cost saving. 6.4.3. Approach The proposed memory BISR design is illustrated in Figure 1.

It consists of three

major components: a memory BIST (MBIST), redundancy wrapper logic, and a fuse box. The description of each logic block is described below.

Figure 5-5: The memory BISR structure [7] The memory BIST consists of a standard memory BIST controller and the redundancy logic interface, which provides the following signals: 27

Expected data which is used to compare the test results from the memory Fail address which stores address of faulty data Fail signal which is used as a write enable for the redundancy logic An on chip memory test runs through the address space of the memory and performs write and read operations according to the test algorithm. The memory output is compared to the expected data. If the words differ, part of the respective memory word is faulty, the faulty address will be stored, and the fail signal is set high to activate redundancy logic. The multiplexer between the MBSIT and the memory is used to provide test patterns generated from MBSIT to the memory.

Figure 5-6: Memory BIST and its interface to the redundancy logic [7] The redundancy logic is placed and accessed in parallel to the memory without spare rows and spare columns.

This avoids unnecessary external or internal redundancy

calculation and does not increase the test time for the memory BIST.

The wrapper logic

consists of two basic components: (1) storage for expected data and faulty address, and (2) address decode and compare logic.

When a faulty word is detected at MBIST, the

address of the faulty word and its corresponding expected data is added to the redundancy logic as long as there is still space left.

Then this expected data that was just stored is

used to read or write instead of the original faulty memory data. This is possible 28

because this redundancy wrapper logic can be designed that is to guaranteed to be faster than a memory array access. An overflow bit identifies that there are more faulty addresses than the wrapper logic can repair. The failing addresses can be read out after the memory test to program fuse boxes.

Figure 5-7: Redundancy wrapper logic with MBIST connected at top [7] A fuse box stores identified failures after memory test.

One fuse carries one

address bit. In normal chip operation, the fuses are probed at power on and their values are stored in feedback structures, e.g., back to back inverters.

The proposed fuse box

contains additional logic to the back to back inverter: a scan flip-flop for controlling and observing the fuse data.

By connecting to a scan register, the fuse box can be used to

stream in and out data during test and redundancy configuration to initialize the redundancy logic.

Figure 5-8: Fuse box and scan flip-flop configuration [7] 29

Other advantages are its flexibility and reusability. procedure doe not need to be changed.

The memory layout generation

The redundancy and BIST logic is fully

parametric, synthesizable and can be therefore prepared for reuse.

It is flexible in the

sense that it can be used with various memory types without spare rows and columns. 6.4.4. Conclusions This paper presents a new memory built-in self-repair concept that uses spare words instead of spare columns and rows.

It uses redundancy logic to perform a software

repair as long as spare words are available when a MBISR test finds failures. Permanent storage of those failing addresses in the field is possible with electrical or field programmable fuses.

7. Future Direction Using memory BIST has various advantages such as no external test equipment, reduced development efforts, at-speed tests.

However, there are many challenges

associated with it such as silicon area overhead, extra pins and routing. In addition, the testability of the test hardware itself is another difficult task. Therefore, based on results of this study, we offer some insights and suggestions for various design parameters that should be taken into consideration when designing next generation memory BIST. A future memory BIST tester should have very short test time since this ultimately determines the final testing cost. We need high-quality test algorithms, those with high coverage which has high correlation to yield. The hardware needs to be simple since this determine the speed and area overhead of the tester. Automatic generation that can ease design efforts will soon demonstrate itself a great value due to the ever increasing 30

time-to-market pressure.

The BIST circuit should posses certain degree of

self-repairability to improve the fault-tolerance and increase reliability. Finally, a flexible BIST that can adapt to engineering and algorithmic changes will greatly reduce system design cost.

8. Conclusions Memory testing is very important but challenging.

Memory BIST is considered the

best solution due to various engineering and economic reasons.

March tests are the

most popular algorithms currently implemented in BIST hardware.

Various

implementation schemes for memory BISTs are presented and their trade-offs are discussed: A Hardwired-based BIST is fast and compact, whereas a Processor-based BIST cost near zero hardware overhead and very flexible. innovations are also surveyed.

Different proposed

Using Defect Coverage not Fault Coverage as our

measure for test quality is revolutionary. Integrating diagnostic capabilities into BIST improves overall system robustness and chip yield. Automatic generation eases design efforts

for

test

integration

and

help

satisfying

time-to-market

requirements.

Self-repairability is the key to fault-tolerant and reliable circuit. In conclusion, the future Memory BIST designs should be fast, small, efficient, robust, and flexible.

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9. References [1] Dongkyu Youn, Taehyung Kim, Sungju Park, “A microcode-based memory BISTimplementing modified march algorithm,” Asian Test Symposium, 2001. Proceedings. 10th, 2001, pp. 391-395 [2] Zarrineh, K. and Upadhyaya, S.J., “On programmable memory built-in self test architectures,” Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings , 1999, pp. 708 -713 [3] Ching-Hong Tsai, and Cheng-Wen Wu, “Processor-programmable memory BIST for bus-connected embedded memories,” Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific , 2001, pp. 325 -330 [4] Jee, A., “Defect-oriented analysis of memory BIST tests,” Memory Technology, Design and Testing, 2002. (MTDT 2002) [5] Hunter, C., “Integrated diagnostics for embedded memory built-in self test on PowerPC™ devices,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1997. (ICCD 1997). Proceedings, 1997. pp. 549-554 [6] Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, “Automatic generation of memory built-in self-test cores for system-on-chip,” Asian Test Symposium, 2001. Proceedings. 10th, 2001, pp. 91-96 [7] Schöber, V.; Paul, S.; Picot, O., “Memory built-in self-repair using redundant words,” International Test Conference, 2001. (ITC 2001). Proceedings, 2001. pp. 995 -1001

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